Apparatus and methods for effective impurity gettering

ABSTRACT

Apparatus and methods for effective impurity gettering are described herein. In some embodiments, a described device includes: a substrate; a pixel region disposed in the substrate; an isolation region disposed in the substrate and within a proximity of the pixel region; and a heterogeneous layer on the seed area. The isolation region comprises a seed area including a first semiconductor material. The heterogeneous layer comprises a second semiconductor material that has a lattice constant different from that of the first semiconductor material.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a division of U.S. patent application Ser. No.16/998,525, filed Aug. 20, 2020, the contents of which is incorporatedby reference in its entirety.

BACKGROUND

Semiconductor image sensors typically include complementarymetal-oxide-semiconductor (CMOS) image sensors (CIS) and charge-coupleddevice (CCD) sensors, which are widely used to sense light in variousapplications such as digital still camera (DSC), mobile phone camera,digital video (DV) and digital video recorder (DVR) applications. Forexample, image sensors can be used for sensing exposed light projectedtoward a semiconductor substrate. CMOS image sensors generally includean active region having an array of light sensitive elements (pixels),and a periphery region. These products utilize an array of active pixels(i.e., image sensor elements or cells) including photodiodes and otherelements (e.g., transistors) to convert images into digital data orelectrical signals.

The photodiodes are characterized by a dark current (DC) or a whitepixel (WP) performance. To improve DC and WP performances, defectcenters have been generated for impurity gettering. In one example,silicon defects are generated, based on e.g. carbon implantation, asgettering centers close to pixels or photodiodes. But these getteringcenters can induce crystal defects and extra leakage in photodiodesnearby, which causes worse DC and WP performances. In another example, abackside poly layer is used as a gettering center to collect metal ionsand defects during thermal process. But the backside poly layer is farfrom the photodiode, e.g. up to hundreds of micrometers. This degradesthe gettering capability, as it is difficult or impossible for metalions in the photodiode to travel that far to the gettering center.

As such, conventional apparatus and methods of impurity gettering havenot been entirely satisfactory in every aspect.

BRIEF DESCRIPTION OF THE DRAWINGS

Various exemplary embodiments of the present disclosure are described indetail below with reference to the following Figures. The drawings areprovided for purposes of illustration only and merely depict exemplaryembodiments of the present disclosure to facilitate the reader'sunderstanding of the present disclosure. Therefore, the drawings shouldnot be considered limiting of the breadth, scope, or applicability ofthe present disclosure. It should be noted that for clarity and ease ofillustration these drawings are not necessarily drawn to scale.

FIG. 1 illustrates a schematic cross-sectional view of a devicecomprising a pixel cell and a gettering center, in accordance with someembodiments of the present disclosure.

FIG. 2 illustrates a schematic cross-sectional view of a latticestructure at an interface of two semiconductor materials, in accordancewith some embodiments of the present disclosure.

FIG. 3A through FIG. 3K are schematic cross-sectional views ofintermediate stages showing a method for manufacturing a devicecomprising at least one pixel cell, in accordance with some embodimentsof the present disclosure.

FIG. 4 illustrates a flow chart of a method for manufacturing a devicecomprising at least one pixel cell, in accordance with some embodimentsof the present disclosure.

FIG. 5A through FIG. 5K are schematic cross-sectional views ofintermediate stages showing another method for manufacturing a devicecomprising at least one pixel cell, in accordance with some embodimentsof the present disclosure.

FIG. 6 illustrates a flow chart of another method for manufacturing adevice comprising at least one pixel cell, in accordance with someembodiments of the present disclosure.

FIG. 7 illustrates a schematic cross-sectional view of another devicecomprising a pixel cell and a gettering center, in accordance with someembodiments of the present disclosure.

FIG. 8 illustrates a schematic cross-sectional view of yet anotherdevice comprising a pixel cell and a gettering center, in accordancewith some embodiments of the present disclosure.

FIG. 9 illustrates a schematic cross-sectional view of still anotherdevice comprising a pixel cell and a gettering center, in accordancewith some embodiments of the present disclosure.

DETAIL DESCRIPTION

Various exemplary embodiments of the present disclosure are describedbelow with reference to the accompanying figures to enable a person ofordinary skill in the art to make and use the present disclosure. Aswould be apparent to those of ordinary skill in the art, after readingthe present disclosure, various changes or modifications to the examplesdescribed herein can be made without departing from the scope of thepresent disclosure. Thus, the present disclosure is not limited to theexemplary embodiments and applications described and illustrated herein.Additionally, the specific order and/or hierarchy of steps in themethods disclosed herein are merely exemplary approaches. Based upondesign preferences, the specific order or hierarchy of steps of thedisclosed methods or processes can be re-arranged while remaining withinthe scope of the present disclosure. Thus, those of ordinary skill inthe art will understand that the methods and techniques disclosed hereinpresent various steps or acts in a sample order, and the presentdisclosure is not limited to the specific order or hierarchy presentedunless expressly stated otherwise.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly. Terms such as“attached,” “affixed,” “connected” and “interconnected,” refer to arelationship wherein structures are secured or attached to one anothereither directly or indirectly through intervening structures, as well asboth movable or rigid attachments or relationships, unless expresslydescribed otherwise.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this disclosure belongs. It willbe further understood that terms, such as those defined in commonly useddictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art and thepresent disclosure, and will not be interpreted in an idealized oroverly formal sense unless expressly so defined herein.

Reference will now be made in detail to the present embodiments of thedisclosure, examples of which are illustrated in the accompanyingdrawings. Wherever possible, the same reference numbers are used in thedrawings and the description to refer to the same or like parts.

The present disclosure provides devices and methods for impuritygettering, where a heterogeneous layer is generated as a getteringcenter within a proximity of a pixel region in an image sensor, e.g. acomplementary metal-oxide-semiconductor (CMOS) image sensor (CIS), toimprove dark current (DC) and white pixel (WP) performances of the imagesensor. The heterogeneous layer is a sacrificed and non-photo-activeregion, and has a super defective structure to collect defects, e.g.metal ions, silicon dot-defects, impurities, etc., in the silicon bulkregion including the pixel region to form device circuits.

In one embodiment, a disclosed device, e.g. an image sensor, includes apixel region disposed in a substrate, and a heterogeneous layerincluding high-density defects near the pixel region. The heterogeneouslayer includes a semiconductor material that has a lattice constantdifferent from that of a semiconductor material in the substrate. Forexample, when the substrate is made of silicon (Si), the heterogeneouslayer may include: germanium (Ge), silicon germanium (SiGe), germaniumtin (GeSn), indium arsenide (InAs), indium antimonide (InSb), siliconcarbide (SiC), silicon borides (SiB), phosphidosilicates (SiP), or anyother semiconductor material that has a lattice mismatch with silicon.The lattice mismatch between the two semiconductor materials inducesdefects such as dislocations or strains generated at thehetero-interfaces and penetrating into the heterogeneous layer. Thestrains and defects induced by the heterogeneous layer are veryeffective for gettering metal ions, silicon dot-defects, and impuritiesof the device after heat treatment, which causes less strains and lessdefects in the silicon region of the substrate.

In one embodiment, the heterogeneous layer is a highly defective layerserving as a gettering center and is very close to the pixel region,damaged shallow trench isolation (STI) and/or damaged photodiodesurface, which are main sources of dark currents and white pixels. Assuch, the heterogeneous layer near the photodiode can attract moredefects from photodiode, to reduce dark currents and white pixels.

At the same time, the generated high-density defects including strainsand dislocations are located only within the heterogeneous layer, butnot in the silicon region of the substrate. That is, the defects anddislocations originate from the highly defective layer and terminate atthe hetero-interfaces, without going outside the highly defective layeror the heterogeneous layer. The defects and dislocations are typicallylocated near the hetero-interfaces and within the heterogeneous layer.Because of this clear and controlled boundary of defects, theheterogeneous layer can be located very close to the photodiode or thephoto-active region to achieve a high gettering efficiency. While thegenerated crystal defects (like strains and dislocations) are confinedin the heterogeneous layer to attract impurity, the crystal defects willnot extend into the silicon region or pixel region to cause damage inthe photodiode. As such, the disclosed device structure can provide aneffective impurity gettering without silicon damages in photodiodes,thereby avoiding the leakage side effect.

According to various embodiments, the heterogeneous layer may bedisposed in the substrate and near the photodiode, above the photodiode,or right on the photodiode. According to some embodiments, the devicealso includes an isolation region, which may be around the heterogeneouslayer or under the heterogeneous layer. In one embodiment, the isolationregion comprises silicon and a dopant, and is configured for isolatingthe heterogeneous layer from charge carriers generated in the substrateof the image sensor. The dopant may have a conductivity type beingn-type or p-type.

FIG. 1 illustrates a schematic cross-sectional view of a semiconductordevice 100 comprising a pixel cell and a gettering center, in accordancewith some embodiments of the present disclosure. In some embodiments,the semiconductor device 100 is a CMOS image sensor device, which may beoperated for sensing incident light.

As shown in FIG. 1, the semiconductor device 100 includes a substrate110, a pixel region 120, an isolation region 130, a heterogeneous layer140, and a transfer gate 150. The substrate 110 may comprise: a group IVmaterial, a group IV material compound, or a group III-V materialcompound. The pixel region 120 is disposed in the substrate 110 and maycomprise a semiconductor material with a dopant. The dopant may have aconductivity type being n-type or p-type. In one embodiment, thesubstrate 110 includes silicon; while the pixel region 120 includesdoped silicon as a light sensitive material.

The portions other than the pixel region 120 in the substrate 110 may bereferred to as a non-pixel region. The transfer gate 150 is disposed onthe non-pixel region of the substrate 110. The pixel region 120 mayinclude a photodiode to sense incident light and enable the substrate110 to generate charge carriers based on photoelectric effect in thepixel region 120. The charge carriers form an electrical current whichis guided by the transfer gate 150 to other devices, such as transistorsor other MOS devices. The transfer gate 150 may be surrounded by aspacer 160. In one embodiment, the transfer gate 150 includes a metal ora conductive material; and the spacer 160 includes a dielectricmaterial, such as silicon oxide, silicon nitride, silicon oxynitride,silicon carbide, or any combinations thereof.

Both the substrate 110 and the pixel region 120 may have metal ions,dot-defects, or other impurities generated during the manufacturing. Theheterogeneous layer 140 is disposed in the substrate 110 and inproximity to the pixel region 120 to provide a gettering of impurities190, e.g. metal ions, dot-defects, or other impurities, in the substrate110 and in the pixel region 120. In one embodiment, the distance betweenthe heterogeneous layer 140 and the pixel region 120 is less than onemicrometer. In another embodiment, the distance between theheterogeneous layer 140 and the pixel region 120 is less than 100nanometers. In yet another embodiment, the distance between theheterogeneous layer 140 and the pixel region 120 is less than 10nanometers.

In the example shown in FIG. 1, the heterogeneous layer 140 is disposedin a trench which has a bottom surface 135. The bottom surface 135 ofthe trench serves as a seed area for epitaxially growing theheterogeneous layer 140 in the trench. That is, the heterogeneous layer140 is grown epitaxially on the seed area 135. In one embodiment, theheterogeneous layer 140 has a depth greater than that of the pixelregion 120.

As shown in FIG. 1, the isolation region 130 is disposed in thesubstrate 110 and within a proximity of the pixel region 120. In oneembodiment, the isolation region 130 is in direct contact with the pixelregion 120. In the example shown in FIG. 1, the heterogeneous layer 140is disposed in a trench that extends into the isolation region 130. Assuch, the isolation region 130 comprises the seed area 135 on which theheterogeneous layer 140 is grown on. As such, the heterogeneous layer140 is surrounded by the isolation region 130 as shown in FIG. 1. In oneembodiment, the isolation region 130 comprises a same semiconductormaterial as the substrate 110, and comprises a dopant configured forisolating the heterogeneous layer 140 from charge carriers generated inthe substrate 110. The dopant may have a conductivity type being n-typeor p-type.

In some embodiments, while the substrate 110 includes a firstsemiconductor material, the heterogeneous layer 140 includes a secondsemiconductor material that has a lattice constant different from thatof the first semiconductor material. In one example, while the substrate110 includes silicon (Si); the heterogeneous layer 140 may include amaterial with a larger lattice constant than silicon, e.g. germanium(Ge), silicon germanium (SiGe), germanium tin (GeSn), indium arsenide(InAs), or indium antimonide (InSb). In another example, while thesubstrate 110 includes silicon (Si); the heterogeneous layer 140 mayinclude a material with a smaller lattice constant than silicon, e.g.silicon carbide (SiC), silicon borides (SiB), or phosphidosilicates(SiP).

FIG. 2 illustrates a schematic cross-sectional view of a latticestructure 200 at an interface of two semiconductor materials 210, 220,in accordance with some embodiments of the present disclosure. As shownin FIG. 2, the lower material 210 may be Si as in the substrate 110 andin the seed area 135 of the isolation region 130 in FIG. 1; and theupper material 220 may be SiGe as in the heterogeneous layer 140 inFIG. 1. As shown in FIG. 2, because there is a lattice mismatch betweenthe two materials Si and SiGe, a dislocation 230 is generated in theupper material 220 and at the interface between the two materials. Theinterface between the two materials may be called a hetero-interface.

Referring back to FIG. 1, due to the lattice match at the seed area 135,the heterogeneous layer 140 induces defects such as dislocations 141 andstrains 142 at the hetero-interface, where the defects or strains canpenetrate into the heterogeneous layer 140. In one embodiment, thestrains, defects and dislocations in the heterogeneous layer 140 arelocated in proximity to the hetero-interfaces. The strains and defectsinduced by the heterogeneous layer 140 are extremely effective forgettering of impurities 190, e.g. metal ions, dot-defects, or otherimpurities, in the substrate 110 and the pixel region 120, especiallyafter heat treatment.

In addition, the strains, defects and dislocations originated within theheterogeneous layer 140 terminate at the hetero-interfaces between theheterogeneous layer 140 and the isolation region 130. That is, thestrains, defects and dislocations are located within the heterogeneouslayer 140, but not within the isolation region 130 or other portions ofthe substrate 110. The clear boundary of the heterogeneous layer 140confines the strains, defects and dislocations within the heterogeneouslayer 140, which ensures that no defect will extend from theheterogeneous layer 140 into the substrate 110 or the pixel region 120to cause silicon damage.

FIG. 3A through FIG. 3K are schematic cross-sectional views ofintermediate stages showing a method for manufacturing a semiconductordevice comprising at least one pixel cell, e.g. the semiconductor device100 in FIG. 1, in accordance with some embodiments of the presentdisclosure. FIG. 3A is a cross-sectional view of the semiconductordevice including a semiconductor substrate 310, which is provided at oneof the various stages of fabrication, according to some embodiments ofthe present disclosure. The semiconductor substrate 310 may be providedto include a group IV material, a group IV material compound, or a groupIII-V material compound. For example, the group IV material may be Si.

FIG. 3B is a cross-sectional view of the semiconductor device includinga pixel region 320, which is formed inside the substrate 310 at one ofthe various stages of fabrication, according to some embodiments of thepresent disclosure. The pixel region 320 may be formed by doping adopant into the substrate 310. The dopant may have a conductivity typebeing n-type or p-type. The remaining portion in the substrate 310 otherthan the pixel region 320 may be referred to as a non-pixel region.

As shown in FIG. 3C, a transfer gate 330 is formed on and in contactwith the non-pixel region of the substrate 310. Optionally, as shown inFIG. 3C, a spacer 335 is formed around the transfer gate 330 on top ofthe substrate 310. In one embodiment, the transfer gate 330 includes ametal or a conductive material; and the spacer 335 includes a dielectricmaterial, such as silicon oxide, silicon nitride, silicon oxynitride,silicon carbide, or any combinations thereof.

As shown in FIG. 3D, a hard mask 340 is deposited on the substrate 310and the pixel region 320, at one of the various stages of fabrication,according to some embodiments of the present disclosure. In oneembodiment, the hard mask 340 may include materials like: silicon oxide,silicon nitride, silicon oxynitride, etc.

In some exemplary examples, as shown in FIG. 3E, a patterned photoresist350 is deposited on the hard mask 340, at one of the various stages offabrication, according to some embodiments of the present disclosure. Inone embodiment, the patterned photoresist 350 may include materials likeSEPR602.

As shown in FIG. 3F, the hard mask 340 is etched to have a patterndetermined based on the patterned photoresist 350, at one of the variousstages of fabrication, according to some embodiments of the presentdisclosure. In the example shown in FIG. 3F, the pattern provides anopening of the hard mask 340 on top of the substrate 310 near the pixelregion 320.

As shown in FIG. 3G, the substrate 310 is etched to form a trench 360based on the patterned photoresist 350 and the hard mask 340, at one ofthe various stages of fabrication, according to some embodiments of thepresent disclosure. In the example shown in FIG. 3G, the trench 360extends from the opening of the hard mask 340 into the substrate 310 andwithin a proximity of the pixel region 320. The distance between thetrench 360 and the pixel region 320 may be less than one micrometer,less than 100 nanometers, or less than 10 nanometers, according tovarious embodiments. The trench 360 has a bottom surface 365 that has asame semiconductor material as the substrate 310.

As shown in FIG. 3H, the patterned photoresist 350 is optionally removedafter forming the trench 360, at one of the various stages offabrication, according to some embodiments of the present disclosure.For example, the patterned photoresist 350 may be removed by using anetching process, a polishing process or a thinning process.

As shown in FIG. 3I, a heterogeneous layer 370 is formed in the trench360 to fill the trench 360, at one of the various stages of fabrication,according to some embodiments of the present disclosure. In the exampleshown in FIG. 3I, the heterogeneous layer 370 is epitaxially grown onthe bottom surface 365 of the trench 360. While the bottom surface 365and the substrate 310 include a first semiconductor material, theheterogeneous layer 370 comprises a second semiconductor material thathas a lattice constant different from that of the first semiconductormaterial. For example, when the first semiconductor material is silicon,the heterogeneous layer 370 may include a material with a larger latticeconstant than silicon, e.g. Ge, SiGe, GeSn, InAs, or InSb; or include amaterial with a smaller lattice constant than silicon, e.g. SiC, SiB, orSiP. Due to the lattice mismatch between the first semiconductormaterial and the second semiconductor material, defects such asdislocations 371 and strains 372 are formed within the heterogeneouslayer 370 and terminate at the hetero-interfaces between theheterogeneous layer 370 and the substrate 310.

As shown in FIG. 3J, the hard mask 340 is optionally removed afterforming the heterogeneous layer 370, at one of the various stages offabrication, according to some embodiments of the present disclosure.For example, the hard mask 340 may be removed by using an etchingprocess, a polishing process or a thinning process. This forms asemiconductor device 300.

In some examples, the heterogeneous layer 370 is formed by epitaxiallygrowing the second semiconductor material with a dopant in the trench.The dopant may have a conductivity type being n-type or p-type. Then asshown in FIG. 3K, the device 300 may be annealed so as to drive thedopant into the substrate 310 to form an isolation region 380 around theheterogeneous layer 370. The heterogeneous layer 370 can provide agettering of impurities 390, e.g. metal ions, dot-defects, or otherimpurities, in the substrate 310 and in the pixel region 320. Theisolation region 380 provides an electrically neutral region forisolating the heterogeneous layer 370 from charge carriers generated inthe substrate 310 based on, e.g. an incident light into the lightsensing materials in the pixel region 320.

FIG. 4 illustrates a flow chart of a method 400 for manufacturing adevice comprising at least one pixel cell, e.g. the semiconductor device100 in FIG. 1, in accordance with some embodiments of the presentdisclosure. The method begins at operation 402, where a substratecomprising a first semiconductor material is provided. At operation 404,a pixel region is formed inside the substrate, where the remainingportion of the substrate other than the pixel region forms a non-pixelregion.

At operation 406, a transfer gate is formed on the non-pixel region ofthe substrate. At operation 408, a hard mask is deposited on thesubstrate. At operation 410, a patterned photoresist is deposited on thehard mask. At operation 412, the hard mask and the substrate are etchedto form a trench extending into the substrate.

At operation 414, the photoresist on the hard mask is removed. Atoperation 416, a second semiconductor material is epitaxially grown witha dopant in the trench to form a heterogeneous layer. The dopant mayhave a conductivity type being n-type or p-type. At operation 418, thehard mask on the substrate is removed to form a device. At operation420, the device is annealed to drive the dopant into the substrate toform an isolation region around the heterogeneous layer.

FIG. 5A through FIG. 5K are schematic cross-sectional views ofintermediate stages showing another method for manufacturing a devicecomprising at least one pixel cell, e.g. the semiconductor device 100 inFIG. 1, in accordance with some embodiments of the present disclosure.The stages of the method shown from FIG. 5A to FIG. 5F are similar tothe stages shown in FIG. 2A to FIG. 2F, respectively. As shown in FIG.5F, the hard mask 540 is etched to provide an opening 551 on top of thesubstrate 510 near the pixel region 520, based on the patternedphotoresist 550.

As shown in FIG. 5G, an isolation region 561 is formed inside thesubstrate 510 by, e.g. doping the substrate 510 with a dopant via theopening 551 to provide the isolation region 561. The dopant may have aconductivity type being n-type or p-type. The isolation region 561 is anelectrically neutral region disposed in the substrate 510 and close tothe pixel region 520.

As shown in FIG. 5H, the isolation region 561 in the substrate 510 isetched to form a trench 560 based on the patterned photoresist 550 andthe patterned hard mask 540, at one of the various stages offabrication, according to some embodiments of the present disclosure. Inthe example shown in FIG. 5G, the trench 560 extends from the opening ofthe hard mask 540 into the isolation region 561 and within a proximityof the pixel region 520. The distance between the trench 560 and thepixel region 520 may be less than one micrometer, less than 100nanometers, or less than 10 nanometers, according to variousembodiments. The trench 560 has a bottom surface 565 that has the samesemiconductor material as the isolation region 561 and the substrate510.

As shown in FIG. 5I, the patterned photoresist 550 is removed, e.g. byusing an etching process, a polishing process or a thinning process.Then as shown in FIG. 5J, a heterogeneous layer 570 is formed in thetrench 560 to fill the trench 560. In the example shown in FIG. 5J, theheterogeneous layer 570 is epitaxially grown on the bottom surface 565of the trench 560. While the bottom surface 565 and the substrate 510include a first semiconductor material, the heterogeneous layer 570comprises a second semiconductor material that has a lattice constantdifferent from that of the first semiconductor material. For example,when the first semiconductor material is silicon, the heterogeneouslayer 570 may include a material with a larger lattice constant thansilicon, e.g. Ge, SiGe, GeSn, InAs, or InSb; or include a material witha smaller lattice constant than silicon, e.g. SiC, SiB, or SiP. Due tothe lattice mismatch between the first semiconductor material and thesecond semiconductor material, defects such as dislocations 571 andstrains 572 are formed within the heterogeneous layer 570 and terminateat the hetero-interfaces between the heterogeneous layer 570 and theisolation region 561 in the substrate 510.

As shown in FIG. 5K, the hard mask 540 is removed, e.g. by using anetching process, a polishing process or a thinning process. This forms asemiconductor device 500. In some examples, the heterogeneous layer 570can provide a gettering of impurities 590, e.g. metal ions, dot-defects,or other impurities, in the substrate 510 and in the pixel region 520.The isolation region 561 is configured for isolating the heterogeneouslayer 570 from charge carriers generated in the substrate 510 based on,e.g. an incident light into the light sensing materials in the pixelregion 520.

FIG. 6 illustrates a flow chart of another method 600 for manufacturinga device comprising at least one pixel cell, e.g. the semiconductordevice 100 in FIG. 1, in accordance with some embodiments of the presentdisclosure. The method begins at operation 602, where a substratecomprising a first semiconductor material is provided. At operation 604,a pixel region is formed inside the substrate, where the remainingportion of the substrate other than the pixel region forms a non-pixelregion.

At operation 606, a transfer gate is formed on the non-pixel region ofthe substrate. At operation 608, a hard mask is deposited on thesubstrate. At operation 610, a patterned photoresist is deposited on thehard mask. At operation 612, the hard mask is etched based on thepatterned photoresist to form an opening of the hard mark on thesubstrate.

At operation 614, the substrate is doped via the opening to form anisolation region in the substrate near the pixel region. At operation616, the isolation region in the substrate is etched to form a trench inthe isolation region. At operation 618, the photoresist on the hard maskis removed. At operation 620, a second semiconductor material isepitaxially grown on a bottom surface of the trench to form aheterogeneous layer. At operation 622, the hard mask on the substrate isremoved to form the device.

FIG. 7 illustrates a schematic cross-sectional view of another device700 comprising a pixel cell and a gettering center, in accordance withsome embodiments of the present disclosure. The device 700 includes asubstrate 710 and a pixel region disposed in the substrate 710. Thepixel region includes: a first light sensing region 721 disposed in thesubstrate 710, and a second light sensing region 722 disposed on thefirst light sensing region 721. In one embodiment, the first lightsensing region 721 comprises a first dopant of a first conductivitytype; and the second light sensing region 722 comprises a second dopantof a second conductivity type different from the first conductivitytype. In one embodiment, the substrate 710 includes silicon; the firstlight sensing region 721 comprises n-type doped silicon to form ann-type photodiode sensor; and the second light sensing region 722comprises p-type doped silicon to form a p-type photodiode sensor. Inone embodiment, the first light sensing region 721 and the second lightsensing region 722 form a p-n junction for transforming photons intoelectrons when the pixel region is exposed to light.

Similar to the device 100 in FIG. 1, the device 700 further includes atransfer gate 750 disposed on the non-pixel region of the substrate 710and surrounded by a spacer 760. Similar to the device 100 in FIG. 1, thedevice 700 includes an isolation region 730 disposed in the substrate710 and within a proximity of the pixel region comprising the firstlight sensing region 721 and the second light sensing region 722. In oneembodiment, the isolation region 730 is in direct contact with the firstlight sensing region 721 and the second light sensing region 722.

As shown in FIG. 7, the device 700 has a heterogeneous layer 740disposed in a trench that extends into the isolation region 730 and hasa bottom surface 735. The bottom surface 735 of the trench serves as aseed area for epitaxially growing the heterogeneous layer 740 in thetrench. The heterogeneous layer 740 is surrounded by the isolationregion 730 as shown in FIG. 7. In one embodiment, the isolation region730 comprises a same semiconductor material as the substrate 710, andcomprises a dopant configured for isolating the heterogeneous layer 740from charge carriers generated in the substrate 710. The dopant may havea conductivity type being n-type or p-type.

Different from the device 100 in FIG. 1, the device 700 in FIG. 7includes a trench isolation 770 extending into the heterogeneous layer740. In one embodiment, the trench isolation 770 is a shallow trenchisolation (STI) structure formed according to a predetermined design. Inone embodiment, the trench isolation 770 comprises a dielectricmaterial, such as silicon oxide, silicon nitride, silicon oxynitride,silicon carbide, or any combinations thereof.

In some embodiments, while the substrate 710 includes a firstsemiconductor material, the heterogeneous layer 740 includes a secondsemiconductor material that has a lattice constant different from thatof the first semiconductor material. As such, there is a lattice matchbetween the first semiconductor material in the isolation region 730 andthe second semiconductor material in the heterogeneous layer 740, whichinduces defects such as dislocations 741 and strains 742 at thehetero-interface, where the defects or strains can penetrate into theheterogeneous layer 740. The strains and defects induced by theheterogeneous layer 740 are effective for gettering of impurities 790,e.g. metal ions, dot-defects, or other impurities, in the substrate 710,the first light sensing region 721, and the second light sensing region722. The strains, defects and dislocations originated within theheterogeneous layer 740 terminate at the hetero-interfaces between theheterogeneous layer 740 and the isolation region 730. That is, thestrains, defects and dislocations are located within the heterogeneouslayer 740, but not within the isolation region 730 or other portions ofthe substrate 710, which ensures that no defect will extend from theheterogeneous layer 740 into other portions of the substrate 710 tocause silicon damage.

FIG. 8 illustrates a schematic cross-sectional view of yet anotherdevice 800 comprising a pixel cell and a gettering center, in accordancewith some embodiments of the present disclosure. The device 800 in FIG.8 has a similar structure to the device 100 in FIG. 1, except that thedevice 800 has a heterogeneous layer 840 disposed above a pixel region820 and right above an isolation region 830. The pixel region 820 andthe isolation region 830 are disposed in the substrate 810, and arelocated next to each other. In one embodiment, while the isolationregion 830 includes silicon as the substrate 810, the heterogeneouslayer 840 is epitaxially grown on a top surface 835 of the isolationregion 830 and includes a material with a larger lattice constant thansilicon, e.g. Ge, SiGe, GeSn, InAs, or InSb, or a material with asmaller lattice constant than silicon, e.g. SiC, SiB, or SiP. Thislattice mismatch at the seed area 835 induces defects such asdislocations 841 and strains 842 within the heterogeneous layer 840, toprovide a gettering of impurities 890, e.g. metal ions, dot-defects, orother impurities, in the substrate 810 and the pixel region 820. Becauseof the clear boundary between the heterogeneous layer 840 and theisolation region 830, the strains, defects and dislocations generateddue to the lattice mismatch are located within the heterogeneous layer840 only, and will not extend into the substrate 810 or the pixel region820 to cause silicon damage.

FIG. 9 illustrates a schematic cross-sectional view of still anotherdevice 900 comprising a pixel cell and a gettering center, in accordancewith some embodiments of the present disclosure. The device 900 in FIG.9 has a similar structure to the device 800 in FIG. 8, except that thedevice 900 has an isolation region 930 on a pixel region 920 that isdisposed in the substrate 910, and has a heterogeneous layer 940 on theisolation region 930. In one embodiment, while the isolation region 930includes silicon as the substrate 910, the heterogeneous layer 940 isepitaxially grown on a top surface 935 of the isolation region 930 andincludes a semiconductor material with a different lattice constant fromsilicon. This lattice mismatch at the seed area 935 induces defects suchas dislocations 941 and strains 942 within the heterogeneous layer 940,to provide a gettering of impurities 990, e.g. metal ions, dot-defects,or other impurities, in the substrate 910 and the pixel region 920.Because of the clear boundary between the heterogeneous layer 940 andthe isolation region 930, the strains, defects and dislocationsgenerated due to the lattice mismatch are located within theheterogeneous layer 940 only, and will not extend into the substrate 910or the pixel region 920 to cause silicon damage.

In some embodiments, a device is disclosed. The device includes: asubstrate; a pixel region disposed in the substrate; an isolation regiondisposed in the substrate and within a proximity of the pixel region;and a heterogeneous layer on the seed area. The isolation regioncomprises a seed area including a first semiconductor material. Theheterogeneous layer comprises a second semiconductor material that has alattice constant different from that of the first semiconductormaterial.

In some embodiments, an image sensor comprising a plurality of pixelcells is disclosed. Each of the plurality of pixel cells includes: asubstrate; a pixel region disposed in the substrate; an isolation regionon the pixel region; and a heterogeneous layer on the isolation region.The isolation region comprises a first semiconductor material. Theheterogeneous layer comprises a second semiconductor material. There isa lattice mismatch between the first semiconductor material and thesecond semiconductor material.

In some embodiments, a method for forming a device comprising at leastone pixel cell is disclosed. The method includes: providing a substratecomprising a first semiconductor material; forming a pixel region insidethe substrate; forming a trench extending into the substrate and withina proximity of the pixel region; and epitaxially growing a heterogeneouslayer on a bottom surface of the trench. The heterogeneous layercomprises a second semiconductor material that has a lattice constantdifferent from that of the first semiconductor material.

While various embodiments of the present disclosure have been describedabove, it should be understood that they have been presented by way ofexample only, and not by way of limitation. Likewise, the variousdiagrams may depict an example architectural or configuration, which areprovided to enable persons of ordinary skill in the art to understandexemplary features and functions of the present disclosure. Such personswould understand, however, that the present disclosure is not restrictedto the illustrated example architectures or configurations, but can beimplemented using a variety of alternative architectures andconfigurations. Additionally, as would be understood by persons ofordinary skill in the art, one or more features of one embodiment can becombined with one or more features of another embodiment describedherein. Thus, the breadth and scope of the present disclosure should notbe limited by any of the above-described exemplary embodiments.

It is also understood that any reference to an element herein using adesignation such as “first,” “second,” and so forth does not generallylimit the quantity or order of those elements. Rather, thesedesignations are used herein as a convenient means of distinguishingbetween two or more elements or instances of an element. Thus, areference to first and second elements does not mean that only twoelements can be employed, or that the first element must precede thesecond element in some manner.

Additionally, a person having ordinary skill in the art would understandthat information and signals can be represented using any of a varietyof different technologies and techniques. For example, data,instructions, commands, information, signals, bits and symbols, forexample, which may be referenced in the above description can berepresented by voltages, currents, electromagnetic waves, magneticfields or particles, optical fields or particles, or any combinationthereof.

A person of ordinary skill in the art would further appreciate that anyof the various illustrative logical blocks, modules, processors, means,circuits, methods and functions described in connection with the aspectsdisclosed herein can be implemented by electronic hardware (e.g., adigital implementation, an analog implementation, or a combination ofthe two), firmware, various forms of program or design codeincorporating instructions (which can be referred to herein, forconvenience, as “software” or a “software module), or any combination ofthese techniques.

To clearly illustrate this interchangeability of hardware, firmware andsoftware, various illustrative components, blocks, modules, circuits,and steps have been described above generally in terms of theirfunctionality. Whether such functionality is implemented as hardware,firmware or software, or a combination of these techniques, depends uponthe particular application and design constraints imposed on the overallsystem. Skilled artisans can implement the described functionality invarious ways for each particular application, but such implementationdecisions do not cause a departure from the scope of the presentdisclosure. In accordance with various embodiments, a processor, device,component, circuit, structure, machine, module, etc. can be configuredto perform one or more of the functions described herein. The term“configured to” or “configured for” as used herein with respect to aspecified operation or function refers to a processor, device,component, circuit, structure, machine, module, signal, etc. that isphysically constructed, programmed, arranged and/or formatted to performthe specified operation or function.

Furthermore, a person of ordinary skill in the art would understand thatvarious illustrative logical blocks, modules, devices, components andcircuits described herein can be implemented within or performed by anintegrated circuit (IC) that can include a digital signal processor(DSP), an application specific integrated circuit (ASIC), a fieldprogrammable gate array (FPGA) or other programmable logic device, orany combination thereof. The logical blocks, modules, and circuits canfurther include antennas and/or transceivers to communicate with variouscomponents within the network or within the device. A processorprogrammed to perform the functions herein will become a speciallyprogrammed, or special-purpose processor, and can be implemented as acombination of computing devices, e.g., a combination of a DSP and amicroprocessor, a plurality of microprocessors, one or moremicroprocessors in conjunction with a DSP core, or any other suitableconfiguration to perform the functions described herein.

If implemented in software, the functions can be stored as one or moreinstructions or code on a computer-readable medium. Thus, the steps of amethod or algorithm disclosed herein can be implemented as softwarestored on a computer-readable medium. Computer-readable media includesboth computer storage media and communication media including any mediumthat can be enabled to transfer a computer program or code from oneplace to another. A storage media can be any available media that can beaccessed by a computer. By way of example, and not limitation, suchcomputer-readable media can include RAM, ROM, EEPROM, CD-ROM or otheroptical disk storage, magnetic disk storage or other magnetic storagedevices, or any other medium that can be used to store desired programcode in the form of instructions or data structures and that can beaccessed by a computer.

In this document, the term “module” as used herein, refers to software,firmware, hardware, and any combination of these elements for performingthe associated functions described herein. Additionally, for purpose ofdiscussion, the various modules are described as discrete modules;however, as would be apparent to one of ordinary skill in the art, twoor more modules may be combined to form a single module that performsthe associated functions according embodiments of the presentdisclosure.

Various modifications to the implementations described in thisdisclosure will be readily apparent to those skilled in the art, and thegeneral principles defined herein can be applied to otherimplementations without departing from the scope of this disclosure.Thus, the disclosure is not intended to be limited to theimplementations shown herein, but is to be accorded the widest scopeconsistent with the novel features and principles disclosed herein, asrecited in the claims below.

What is claimed is:
 1. A method for forming a device comprising at leastone pixel cell, comprising: providing a substrate comprising a firstsemiconductor material; forming a pixel region inside the substrate;forming a trench extending into the substrate and within a proximity ofthe pixel region; and epitaxially growing a heterogeneous layer on abottom surface of the trench, wherein the heterogeneous layer comprisesa second semiconductor material that has a lattice constant differentfrom that of the first semiconductor material.
 2. The method of claim 1,wherein forming the trench comprises: depositing a hard mask on thesubstrate; depositing a patterned photoresist on the hard mask; andetching the substrate to form the trench based on the patternedphotoresist and the hard mask.
 3. The method of claim 1, furthercomprising doping the substrate to form an isolation region inside thesubstrate and within a proximity of the pixel region, wherein: thetrench is formed in the isolation region; the heterogeneous layerprovides a gettering of at least one of metal ions, dot-defects, orimpurities in the substrate; and the isolation region is configured forisolating the heterogeneous layer from charge carriers generated in thesubstrate.
 4. The method of claim 1, wherein epitaxially growing theheterogeneous layer comprises: epitaxially growing the secondsemiconductor material with a dopant in the trench.
 5. The method ofclaim 4, wherein epitaxially growing the heterogeneous layer furthercomprises: annealing the device so as to drive the dopant into thesubstrate to form an isolation region around the heterogeneous layer,wherein the dopant has a conductivity type being n-type or p-type. 6.The method of claim 1, further comprising depositing an oxide materialon the heterogeneous layer to form a trench isolation structure withinthe trench.
 7. A method, comprising: providing a substrate; forming apixel region in the substrate; forming an isolation region in thesubstrate and within a proximity of the pixel region, wherein theisolation region comprises a seed area including a first semiconductormaterial; forming a trench structure extending into the isolationregion, wherein the trench structure is on the seed area and not incontact with the pixel region; and filling the trench structure on theseed area with a heterogeneous layer, wherein the heterogeneous layercomprises a second semiconductor material that has a lattice constantdifferent from that of the first semiconductor material.
 8. The methodof claim 7, wherein strains, defects and dislocations originate withinthe heterogeneous layer and terminate at hetero-interfaces between theheterogeneous layer and the isolation region.
 9. The method of claim 8,wherein the strains, defects and dislocations are located in proximityto the hetero-interfaces.
 10. The method of claim 7, wherein theheterogeneous layer provides a gettering of at least one of metal ions,dot-defects, or impurities in the substrate.
 11. The method of claim 7,wherein the heterogeneous layer has a depth greater than that of thepixel region.
 12. The method of claim 7, wherein: the isolation regioncomprises the first semiconductor material and a dopant and isconfigured for isolating the heterogeneous layer from charge carriersgenerated in the substrate; and the dopant has a conductivity type beingn-type or p-type.
 13. The method of claim 7, wherein the heterogeneouslayer is disposed above the pixel region.
 14. The method of claim 7,wherein the pixel region comprises: a first light sensing regiondisposed in the substrate and comprising a first dopant of a firstconductivity type; and a second light sensing region disposed on thefirst light sensing region and comprising a second dopant of a secondconductivity type.
 15. A method, comprising: providing a substrate;forming a pixel region in the substrate, wherein the remaining portionof the substrate other than the pixel region forms a non-pixel region;forming an isolation region in the non-pixel region of the substrate andwithin a proximity of the pixel region, wherein the isolation regioncomprises a seed area including a first semiconductor material; andforming a heterogeneous layer on the seed area in the isolation region,wherein the heterogeneous layer has a depth greater than that of thepixel region, wherein the heterogeneous layer comprises a secondsemiconductor material that has a lattice constant different from thatof the first semiconductor material.
 16. The method of claim 15, whereinstrains, defects and dislocations originate within the heterogeneouslayer and terminate at hetero-interfaces between the heterogeneous layerand the isolation region.
 17. The method of claim 15, wherein thestrains, defects and dislocations are located in proximity to thehetero-interfaces.
 18. The method of claim 15, wherein the heterogeneouslayer provides a gettering of at least one of metal ions, dot-defects,or impurities in the substrate.
 19. The method of claim 15, wherein: theisolation region comprises the first semiconductor material and a dopantand is configured for isolating the heterogeneous layer from chargecarriers generated in the substrate; and the dopant has a conductivitytype being n-type or p-type.
 20. The method of claim 15, wherein thepixel region comprises: a first light sensing region disposed in thesubstrate and comprising a first dopant of a first conductivity type;and a second light sensing region disposed on the first light sensingregion and comprising a second dopant of a second conductivity type.